The present invention relates to a semiconductor memory device in which volatile and non-volatile semiconductor memories are combined.
Recently, the inventor of the present invention and other have proposed a semiconductor memory device of such a type in a U.S. patent application Ser. No. 07/308,854 U.S. Pat. No. 5,075,888. The semiconductor memory device is constructed with a DRAM (dynamic random access memory) which is a volatile semiconductor memory, an EEPROM (electrically erasable/programmable read only memory) which is a non-volatile semiconductor memory, and a mode selector transistor for selecting between the DRAM mode in which the memory device functions as a DRAM and the EEPROM mode in which the memory device functions as an EEPROM. The DRAM typically has a MOS (metal oxide semiconductor) transistor having a gate terminal connected to a word line and a drain terminal connected to a bit line, a sense amplifier, and a capacitor. The EEPROM includes a MOS transistor having a control gate and a floating gate. In this semiconductor memory device, the three transistors are connected successively in series, and one terminal of the capacitor is connected between the MOS transistors of the DRAM and EEPROM. Furthermore, the control gate of the EEPROM and the gate of the mode selector transistor are linked to form a single gate terminal. When a specified voltage is applied to the other terminal of the capacitor or to the linked gate terminal, the accumulated charge in the floating gate of the MOS transistor in the EEPROM is changed, the data in the DRAM is transferred to the EEPROM, and the memory mode of the semiconductor memory device is thus changed.
However, in this semiconductor memory device, when the data in the EEPROM is required to be initialized, that is, when the data in the EEPROM is required to be set to a predetermined initial value of "1" or "0" irrespective of the data in the DRAM, the data held by the DRAM capacitor is destroyed because the applied charge also travels through the DRAM, which is connected to the EEPROM in series. In other words, when the data stored in the DRAM is destroyed before the EEPROM is erased.